FIG. 1 is a block diagram illustrating an access control circuit of conventional single port memory, and as shown in FIG. 1, an access control circuit 100 includes a controller 110 and a memory 120. The memory 120 includes an address decoder and a data output buffer.
The memory 20 is a single port memory, includes a single input port for an access, and a single output port for a data output, Thus, a clock signal output terminal of the controller 110 is coupled to the input port of the memory 120 in one to one.
In a read mode, the controller 110 outputs a clock signal CLK having a predetermined shape to the clock signal output terminal. Herein, the memory 120 outputs the data stored in a corresponding address according to the clock signal CLK provided from the controller 110 through the input port. The data DOUT outputted from the output port of the memory 120 is inputted to the data input port of the controller 110.
In a write mode, the controller 110 outputs the data DIN to the memory 120 and stores the data DIN in a corresponding address,
In a case that a dual port read access is performed in a memory 120 having a single port structure as described above, according to how much time difference between two clock signals inputted from the controller 110 to the memory 120, a signal may be overlapped in an address decoder and a data output buffer included in the memory 120.
Because of the reason described above, in case that a dual port read access is, performed in a memory having a single port structure, a read fail occurs and a normal read access is impossible. Thus, there are problems that a single port memory may be not applied to a DDI that needs an operation of a high performance.